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ucb-bar/gemmini

Hardware & IoT

A full-stack DNN accelerator generator for RISC-V SoCs, aimed at computer-architecture researchers and hardware engineers.

1,555
305
Scala
NOASSERTION
8 years old

Project Overview

Gemmini is a full-system, full-stack exploration and evaluation platform for deep neural network hardware. It is implemented as a RoCC accelerator with custom RISC-V instructions using the Chisel hardware description language, and is part of the Chipyard ecosystem ucb-bar/gemmini. The project targets architects and hardware engineers who want to understand how accelerator design, memory hierarchy, software stack and dataflow choices interact to affect DNN performance.

The accelerator centers on a two-tier systolic array for matrix multiplication, backed by an explicitly managed banked scratchpad and a separate accumulator SRAM with adders, scalers and activation units. A decoupled access/execute architecture splits execute, load and store controllers, with a reorder buffer resolving cross-controller hazards. Two DMAs move data using virtual addresses through a private TLB. CISC-style loop instructions automatically tile and unroll matmuls and convolutions larger than the systolic array README architecture notes.

Configuration parameters control array dimensions (tileRows, tileColumns, meshRows, meshColumns), dataflow (output-stationary, weight-stationary, or runtime-selectable), scratchpad/accumulator capacity and bank count, element datatypes, queue depths, and DMA bus width. Optional features include scaling during move-in and configurable activation functions.

Quick Start

Gemmini is developed inside Chipyard, so the first step is to satisfy the Chipyard dependency requirements. Then clone Chipyard, run its setup script, source the environment, and install the Gemmini software library from the in-tree generator directory:

git clone https://github.com/ucb-bar/chipyard.git
cd chipyard
./build-setup.sh
source env.sh
cd generators/gemmini
make -C software/libgemmini install

Build the test programs, which include small matrix tests and DNN workloads such as ResNet50:

cd chipyard/generators/gemmini/software/gemmini-rocc-tests
./build.sh

The resulting RISC-V binaries land in build/ in baremetal, Linux and proxy-kernel variants README lines 49–52. Build a cycle-accurate Verilator simulator and run a small baremetal workload on it:

cd chipyard/sims/verilator
make CONFIG=GemminiRocketConfig
make CONFIG=GemminiRocketConfig run-binary BINARY=../../generators/gemmini/software/gemmini-rocc-tests/build/bareMetalC/template-baremetal

For faster functional-only runs, use the Gemmini-enabled Spike extension README lines 95–106. The MLSys 2022 tutorial covers building custom accelerators, adding datatypes, writing programs and profiling tutorial.

Usage Constraints

Binary variants are not interchangeable. Linux binaries are dynamically linked and need a Linux-capable SoC; baremetal binaries assume no OS and no virtual memory; proxy-kernel binaries rely on the RISC-V Proxy Kernel and have limited heap space, so some programs that work in the other modes may fail riscv-pk. Cycle-accurate simulation of large DNN workloads can take days, which is why FireSim FPGA-accelerated simulation is recommended for end-to-end runs FireSim. Certain transpose and dataflow combinations are illegal, as documented in the config_ex permission table config_ex. The loop instructions and max-pooling support are marked experimental and subject to change. The repository license is listed as NOASSERTION, so license terms should be confirmed before reuse. Hardware and software are built as part of Chipyard, so matching Chipyard commits matters.

HotRepo's take

Gemmini has no recorded entry in HotRepo's all-language daily rank or star snapshots, so there is no measured popularity trend to report here. What the materials do establish is a long-running academic project (created in 2018) with a substantial 1,555 stars and 305 forks, anchored in Berkeley's Chipyard ecosystem and backed by a DAC 2021 paper citation block. Its value is as a research and evaluation vehicle: the generator exposes dataflow, datatype and memory parameters that make side-by-side architecture experiments practical, while the included ISA-level tests give a concrete starting point for reproducing those experiments.

Written by AI from the project's README, updated . The project's own docs are the source of truth.