YosysHQ/yosys

Yosys is worth your time if you work in digital design and want a scriptable, open synthesis engine you can inspect and extend. It is not a drop-in replacement for a vendor toolchain, but it is a practical centerpiece for open hardware flows.

The problem

You have RTL written in Verilog or SystemVerilog and you need to know whether it maps to real cells in a target library, not just whether the file parses. With a closed synthesizer that step is often a black box: you push files in, get a netlist out, and have limited visibility into how processes, memories and finite-state machines became gates. Yosys changes that step by putting the transformation in your hands, pass by pass, in a script or an interactive shell. The result is a netlist you can inspect, and a recipe you can rerun and modify.

What's different

Yosys is a framework rather than a fixed pipeline. Synthesis is expressed as a sequence of passes, and the README's examples show the progression directly: elaborate with read -sv and hierarchy, convert always blocks with proc, optimize, map to internal cells with techmap, then map flip-flops and logic to a Liberty file using dfflibmap and abc. Because each step is a named command, you can stop after elaboration, dump RTLIL, or swap in your own ordering. The documented synth and prep commands package sensible defaults for gate mapping and word-level work respectively, so beginners are not forced to assemble every pass by hand.

The extension story is the real differentiator: the README explicitly says Yosys can be adapted by combining passes and adding new ones in C++. That cuts both ways. A scriptable pass-based flow gives you an auditable path from source to netlist and makes it possible to target different cell libraries with the same front end. It also means the tool assumes you understand what the passes do; it is a framework for people building a flow, not a single button. Verilog-2005 support is described as extensive, while SystemVerilog support relies on sv-elab and slang and covers an informally defined synthesizable subset of IEEE 1800-2017 or 1800-2023, so "SystemVerilog support" deserves careful reading rather than assuming arbitrary testbench code will synthesize.

Who should try it

Good fit: an engineer or researcher doing open ASIC work, teaching digital design, or building an automated RTL-to-netlist pipeline who needs to script and inspect each synthesis step. Also a good fit for someone using the wider open CAD stack for formal flows, since SBY is the documented formal front-end.

Poor fit: a designer who wants push-button synthesis of a large SystemVerilog design and expects a vendor-grade front end. The project's own materials point to the Tabby CAD Suite for industry-grade SystemVerilog and VHDL parsers, which indicates where the free tool's front end ends. Also a poor fit if you only want linting: the README says read_verilog does not perform syntax checking and recommends linting with another tool such as Verilator first.

Requirements and limitations

There are two setup paths. The easiest is a binary suite, either the free OSS CAD Suite or the commercial Tabby CAD Suite, with linked install instructions. The other is building from source, which requires a long list of libraries (including clang, bison, flex, Tcl, zlib, libffi and graphviz) and fetching submodules. The official flow uses CMake presets and a separate test command, so plan for a real toolchain rather than a single package install. Before depending on a distro package, note the README's warning that Linux distributions vary in how up to date their Yosys binary is.

The ongoing constraints are the cell library and the language subset. To map to real hardware you supply a Liberty file; the README points to free standard-cell libraries for experimentation, and the workflow is only meaningful relative to the library you choose. SystemVerilog is a synthesizable subset, not the whole language, and Verilog linting is explicitly out of scope. There is no claim of coverage for every construct in a large design.

HotRepo's take

HotRepo's only recorded observation is a single daily-board appearance on 2026-10-25 at 4,840 stars, +5 that day. With one date and no earlier history, persistence or momentum cannot be judged, and the number says nothing about synthesis quality. The project itself dates to 2013, so this is an established codebase rather than a novelty. Before adopting it, check whether your SystemVerilog constructs fall inside the documented synthesizable subset and whether a Liberty file exists for your target library; those two points decide whether the flow is usable at all.

Project source and documentation